Assertion-based Design
The Power of Assertions in SystemVerilog
A Practical Guide for SystemVerilog Assertions
Introduction to PSL
Principles of Verifiable RTL Design A Functional Coding Style Supporting Verification Processes in Verilog
Creating Assertion-Based IP
Generating Hardware Assertion Checkers For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
SVA: The Power of Assertions in SystemVerilog
SystemVerilog Assertions and Functional Coverage Guide to Language, Methodology and Applications
Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes